1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly relates to a method of forming trench isolation with enhanced insulating characteristics thereof and structure formed thereby.
2. Description of the Related Art
The technology of isolating devices that are built on a semiconductor substrate becomes one important aspect of the industry of the integrated circuits. Improper device isolation will cause current leakages, which can consume significant power for the entire chip. In addition, improper device isolation can further escalate latch-up to damage the circuit's function momentarily or permanently. Still further, improper device isolation can produce noise margin degradation, voltage shift or crosstalk.
The conventional LOCOS (local oxidation of silicon) process is used to form regions which laterally isolate the active device regions in the integrated circuits. The LOCOS structure is typically formed by using a patterned silicon nitride layer together with a pad oxide underneath, which is utilized to relieve stress caused by the silicon nitride layer, to mask the active regions, followed by ion-implantation in the isolation region, and then growing a thick field oxide locally.
The structure mentioned above possesses some inherent drawbacks resulting from the processes, i.e., lateral oxidation of the silicon underneath the silicon nitride mask, making the edge of the field oxide which resembles the shape of a bird's beak, and the lateral diffusion of channel-stop dopants, making the dopants encroach into the active device regions, making the physical channel width less than the desired channel width. The reduced portion overtaken by both effects will make the situation even worse when devices are scaled down for very large scale integration (VLSI) implementation, increasing the threshold voltage and reducing the current driving capability.
According to the disadvantage mentioned above for the LOCOS isolation structure, an isolation technique by using a shallow trench has been developed. Generally, the shallow trench isolation (hereinafter referred to “STI”) includes the steps of etching a silicon substrate to form a trench; and depositing a CVD oxide layer to fill up the trench; and planarization-etching the CVD oxide layer.
FIGS. 1A to 1E schematically show cross-sectional views of the process steps of a prior art method of forming trench isolation in a semiconductor substrate. Referring to FIG. 1A, a pad oxide layer 3, a nitride layer 4, an HTO (high temperature oxidation) oxide layer 5, and an ARL (anti-reflective layer) 6 are sequentially formed over the semiconductor substrate 2. A photoresist layer pattern 10 is formed over the ARL 6 to define a trench forming area. Using this patterned photoresist layer 10 as a mask, in order the ARL 6, HTO oxide layer 5, silicon nitride layer 4, and pad oxide layer 3 are etched to form a trench mask 8, exposing the semiconductor substrate (2).
After removing the patterned photoresist layer 10, the semiconductor substrate 2 is etched to form a trench 12 therein as shown in FIG. 1B. Preferably, the ARL 6 is concurrently removed. In order to remove substrate damage produced during the aforementioned etching process, a thermal oxide layer 14 is formed on interior walls of the trench 12, i.e., on bottom and both sidewalls of the trench as shown in FIG. 1C.
Referring to FIG. 1D, the remainder of the trench is completely filled with a dielectric layer such as a USG layer (undoped silicate glass layer) 15 extending on the trench mask (8a). A PE-TEOS (plasma enhanced tetra ethyl ortho silicate) oxide layer 16 is subsequently formed thereon to relieve the stress of the USG layer 15. A planarization process is carried out down to the nitride layer 4 and thereby the trench isolation 18 is produced as shown in FIG. 1E. Subsequently the nitride layer 4 and the pad oxide layer 3 are removed by a suitable method.
However, in the STI method, a known problem has been that of stress caused by the dielectric layer, such as the USG layer 15, filled in the trench on the semiconductor substrate. Furthermore, additional stress is applied to the interior walls of the trench 12 during a later oxidation process such as gate oxide layer formation. In other words, the trench interior walls are subjected to being oxidized, and the oxide layer thus formed causes stress resulting from volume expansion. Such stress causes micro defects i.e., dislocation due to damage of the silicon lattice, or shallow pits on the bottom and sidewalls of the trench, and on the active region of the semiconductor substrate, thereby increasing current leakage, constantly putting the source and drain electrodes of the transistor in a “turned-on” state and, in addition, causing a thinning phenomenon for the gate oxide layer on the edge of the active region in the semiconductor substrate, which degrades the insulating characteristics of the trench isolation.
U.S. Pat. No. 5,447,884, entitled “Shallow Trench Isolation with Thin Nitride Layer” illustrated a silicon nitride liner on the thermal oxide layer that is used to relieve the stress.
In order to uniformly fill a dielectric layer in the trench, plasma processing is carried out conventionally on the interior walls of the trench. However, due to plasma processing in down-stream mode, the silicon nitride layer as a stress relief layer is subjected to being etched or damaged, which is not compatible with the aims of the silicon nitride layer.
Accordingly, the prior art method mentioned by the patent cannot avoid the above problems.